By John M. Cohn, David J. Garrod, Visit Amazon's Rob A. Rutenbar Page, search results, Learn about Author Central, Rob A. Rutenbar, , L. Richard Carley
This ebook offers an in depth precis of study on computerized structure of device-level analog circuits that used to be undertaken within the past due Eighties and early Nineteen Nineties at Carnegie Mellon college. We specialise in the paintings at the back of the production of the instruments known as KOAN and ANAGRAM II, which shape a part of the middle of the CMU ACACIA analog CAD method. KOAN is a tool placer for customized analog cells; ANANGRAM II an in depth quarter router for those analog cells. we try to offer the motivations at the back of the structure of those instruments, together with designated dialogue of the delicate know-how and circuit issues that needs to be addressed in any profitable analog or mixed-signal structure device. Our method in organizing the chapters of the ebook has been to offer our algo rithms as a chain of responses to those very actual and intensely tricky analog structure difficulties. eventually, we current various examples of effects generated via our algorithms. This examine used to be supported partly by means of the Semiconductor learn Corpora tion, via the nationwide technology starting place, via Harris Semiconductor, and by means of the foreign enterprise Machines company Resident learn application. eventually, only for the list: John Cohn used to be the clothier of the KOAN placer; David Garrod was once the fashion designer of the ANAGRAM II router (and its predeces sor, ANAGRAM I). This publication was once architected by way of all 4 authors, edited by means of John Cohn and Rob Rutenbar, and produced in accomplished shape by way of John Cohn.
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Additional info for Analog Device-Level Layout Automation
B) KOAN and ANAGRAM II. analog-specific layout constraints. We begin this chapter justifying the use of the flat Gellatt-Jepsen simulated annealing model is the appropriate choice for optimization of analog device placement. We then introduce the simple device generation formulation which supports our model of dynamic device merging and describe the basic placement mechanisms which underlie the analog-specific extensions introduced in later chapters. to verify the robustness of the basic digital-style placer, we produce layouts of two synthetic examples with known optimal answers.
While these techniques are not necessarily unique to our research, they are combined into a framework which is well suited to handle the analog-specific functionality we introduce in subsequent chapters. We show that the design of the basic digital-style placer involves several important technical choices, the most important being the decision to adopt the flat Gellatt-Jepsen annealing style. 2 SIMULATED ANNEALING FOR DEVICE-LEVEL PLACEMENT We have chosen to base our layout optimization on simulated annealing, but this is just one of the methods which have been successfully applied to VLSI placement.
All of the analog layout systems which have been reported rely heavily on Basic Placement 29 the quality of their module generator library for the quality of their layouts [87, 52, 1, 33]. In addition to creating layouts for individual devices, these systems use procedural generation ideas [87, 43] to create layouts for a wide range of frequently encountered multi-device sub-circuits. For example, ILAC , SALIM , OPASYN , and LAMP  all support module generators for differential-pairs, current mirrors, and cascode structures.